<?xml version="1.0" encoding="UTF-8"?><xml><records><record><source-app name="Biblio" version="7.x">Drupal-Biblio</source-app><ref-type>17</ref-type><contributors><authors><author><style face="normal" font="default" size="100%">Dendouga Abdelghani</style></author><author><style face="normal" font="default" size="100%">Slimane, Oussalah</style></author></authors></contributors><titles><title><style face="normal" font="default" size="100%">Comparative Analysis of Two Op-Amp Topologies for a 40MS/s 8-bitPipelined ADC in 0.18μm CMOS Technology, ISSN / e-ISSN 1790-5052 / 2224-3488</style></title><secondary-title><style face="normal" font="default" size="100%">WSEAS TRANSACTIONS ON SIGNAL PROCESSINGWSEAS TRANSACTIONS ON SIGNAL PROCESSING</style></secondary-title></titles><dates><year><style  face="normal" font="default" size="100%">2017</style></year><pub-dates><date><style  face="normal" font="default" size="100%">2017</style></date></pub-dates></dates><volume><style face="normal" font="default" size="100%">Volume 13</style></volume><pages><style face="normal" font="default" size="100%">pp 83-89</style></pages><language><style face="normal" font="default" size="100%">eng</style></language><abstract><style face="normal" font="default" size="100%">The performances of two full differential operational amplifiers (Op-Amps) telescopic and folded-cascode are evaluated to satisfy the stringent requirements on the amplifier to be used in a Multiplying Digital-to-Analog Converter (MDAC) stage of a pipelined ADC (Analog-to-Digital Converter). The paper shows the solutions found to reach high gain, wide bandwidth and short settling time without degrading too much the output swing. The Op-Amp specifications are extracted according to the ADC requirements, then the two Op-Amp topologies are designed, tested and their performances are compared. Simulation results show that the Op-Amp folded-cascode topology is more suitable architecture for pipelined ADC than the telescopic one. Moreover, the use of this type of Op-Amp generates an Integral Non-Linearity (INL) error less than that of the telescopic one. The analyses and simulation results are obtained using 0.18 µm AMS (Austria Mikro System) CMOS process parameters with a power supply voltage of 1.8V. The predicted performance is verified by analysis and simulations using Cadence EDA simulator.</style></abstract></record></records></xml>