Multi-Gate Junctionless MOSFETs are promising devices to overcome the undesired short channel effects for low cost nanoelectronic applications. However, the high series resistance associated to the source and drain extensions can arise as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance. Therefore, in order to obtain a global view of Double-Gate Junctionless (DGJ) MOSFET performance under critical conditions, new designs and models of nanoscale DGJ MOSFET including analog performance are important for the comprehension of the fundamentals of such device characteristics. In the present paper, a numerical investigation for the drain current and small signal characteristics is conducted for the DGJ MOSFET by including highly doped extension regions. The proposed approach, which is from a practical viewpoint a feasible technique by introducing only one ion implantation step, provides a good solution to improve the drain current, small signal parameters, analog/RF behavior and linearity of DGJ MOSFET for high performance analog applications. In this context, I–V and analog characteristics of the proposed design are investigated by 2-D numerical modeling and compared with conventional DGJ MOSFET characteristics.

The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current, ION/IOFF current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.

The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current, ION/IOFF current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.

The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current, ION/IOFF current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.

The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current, ION/IOFF current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.

In this paper, the analytical investigation of a new design including drain and source extensions is presented to assess the electrical behavior of cylindrical gate-all-around junctionless (GAAJ) MOSFET for high performance RF and analog applications. Analytical models for drain current and performance parameters are derived incorporating the effect of two highly doped extension regions. Various analog and RF parameters like transconductance, cut-off frequency, drain current drivability, voltage gain and linearity characteristics have also been investigated. The proposed design shows excellent ability in improving the analog performance and provides a good solution to enhance the RF behavior and linearity of GAAJ MOSFET for low cost and high performance analog/RF applications. The proposed model results have been validated against the data obtained from a commercially available numerical device simulator. Moreover, the developed analytical approaches are easy to be implemented into microelectronic software simulators and therefore allow the study of the GAAJ-based deep submicron circuits

In this paper, the analytical investigation of a new design including drain and source extensions is presented to assess the electrical behavior of cylindrical gate-all-around junctionless (GAAJ) MOSFET for high performance RF and analog applications. Analytical models for drain current and performance parameters are derived incorporating the effect of two highly doped extension regions. Various analog and RF parameters like transconductance, cut-off frequency, drain current drivability, voltage gain and linearity characteristics have also been investigated. The proposed design shows excellent ability in improving the analog performance and provides a good solution to enhance the RF behavior and linearity of GAAJ MOSFET for low cost and high performance analog/RF applications. The proposed model results have been validated against the data obtained from a commercially available numerical device simulator. Moreover, the developed analytical approaches are easy to be implemented into microelectronic software simulators and therefore allow the study of the GAAJ-based deep submicron circuits

In this paper, the analytical investigation of a new design including drain and source extensions is presented to assess the electrical behavior of cylindrical gate-all-around junctionless (GAAJ) MOSFET for high performance RF and analog applications. Analytical models for drain current and performance parameters are derived incorporating the effect of two highly doped extension regions. Various analog and RF parameters like transconductance, cut-off frequency, drain current drivability, voltage gain and linearity characteristics have also been investigated. The proposed design shows excellent ability in improving the analog performance and provides a good solution to enhance the RF behavior and linearity of GAAJ MOSFET for low cost and high performance analog/RF applications. The proposed model results have been validated against the data obtained from a commercially available numerical device simulator. Moreover, the developed analytical approaches are easy to be implemented into microelectronic software simulators and therefore allow the study of the GAAJ-based deep submicron circuits

In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.

In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.

In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.

In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.