We present in this paper a method for optimizing the design of CMOS bandgap voltage reference. The purpose of this work is to provide an optimal devices sizing, to reach the bandgap reference desired performances. This is achieved by using a simple mathematic calculations, basic layout design rules and simulation analyses. The proposed method is applied to design a voltage reference using CMOS 0.35uM process, featuring low temperature coefficient over the range of 105 °C, low noise, good power supply rejection in the range: 2.9 to 3.6 V, and keep an acceptable variation of the nominal value for a different process corners.

We present in this paper a method for optimizing the design of CMOS bandgap voltage reference. The purpose of this work is to provide an optimal devices sizing, to reach the bandgap reference desired performances. This is achieved by using a simple mathematic calculations, basic layout design rules and simulation analyses. The proposed method is applied to design a voltage reference using CMOS 0.35uM process, featuring low temperature coefficient over the range of 105 °C, low noise, good power supply rejection in the range: 2.9 to 3.6 V, and keep an acceptable variation of the nominal value for a different process corners.

We present in this paper a method for optimizing the design of CMOS bandgap voltage reference. The purpose of this work is to provide an optimal devices sizing, to reach the bandgap reference desired performances. This is achieved by using a simple mathematic calculations, basic layout design rules and simulation analyses. The proposed method is applied to design a voltage reference using CMOS 0.35uM process, featuring low temperature coefficient over the range of 105 °C, low noise, good power supply rejection in the range: 2.9 to 3.6 V, and keep an acceptable variation of the nominal value for a different process corners.