Gate‐engineering‐based approach to improve the nanoscale DG MOSFET behavior against interfacial trap effects

Citation:

Bentrcia T, DJEFFAL F, Arar D, Dibi Z. Gate‐engineering‐based approach to improve the nanoscale DG MOSFET behavior against interfacial trap effects. physica status solidi (c)physica status solidi (c). 2014;11 :77-80.

Date Published:

2014

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