Date Published:

Abstract:

In the last few years, an accelerated trend toward the miniaturization of nanoscale circuits has been recorded. In fact, this has been reflected by numerous enhancements at different levels of multi-gate structures such as the channel body or the gate material. Our aim in this work is to investigate the reliability performance of junctionless DG MOSFET including graded channel aspect. The behavior of the considered device is analyzed numerically using ATLAS-2D simulator, where degradation phenomena are accounted for in the model. The variation of some analog/RF criteria namely the transconductance and cut-off frequency are established in terms of the channel length and traps density. The obtained responses indicate the superior immunity of the graded channel device against traps-induced degradation in comparison to the conventional structure. Thus, this work can offer more insights regarding the benefit of adopting the channel doping engineering for future nanoscale electronic applications.