In this paper, we propose a potential high efficiency Cu2ZnSn(S,Se)4/CdS (CZTS) solar cell design based on graded band-gap engineering that can offer the benefits of improved absorption behavior and reduced recombination effects. Moreover, a new hybrid approach based on analytical modeling and Particle Swarm Optimization (PSO) is proposed to determinate the optimal band-gap profile of the amended CZTS absorber layer to achieve further efficiency enhancement. It is found that the proposed design exhibits superior performance, where a high efficiency of 16.9% is recorded for the optimized solar cell with a relative improvement of 92%, compared with the reference cell efficiency of 8.8%. Likewise, the optimized CZTS solar cell with a graded band-gap enables achieving a higher open circuit voltage of 889 mV, a short-circuit current of 28.5 mA and a fill factor of 66%. Therefore, the optimized CZTS-based solar cell with graded-band gap paradigm pinpoints a new path toward recording high-efficiency thin-film solar cells through enhancing carrier collection and reducing the recombination rate.

In this paper, we propose a potential high efficiency Cu2ZnSn(S,Se)4/CdS (CZTS) solar cell design based on graded band-gap engineering that can offer the benefits of improved absorption behavior and reduced recombination effects. Moreover, a new hybrid approach based on analytical modeling and Particle Swarm Optimization (PSO) is proposed to determinate the optimal band-gap profile of the amended CZTS absorber layer to achieve further efficiency enhancement. It is found that the proposed design exhibits superior performance, where a high efficiency of 16.9% is recorded for the optimized solar cell with a relative improvement of 92%, compared with the reference cell efficiency of 8.8%. Likewise, the optimized CZTS solar cell with a graded band-gap enables achieving a higher open circuit voltage of 889 mV, a short-circuit current of 28.5 mA and a fill factor of 66%. Therefore, the optimized CZTS-based solar cell with graded-band gap paradigm pinpoints a new path toward recording high-efficiency thin-film solar cells through enhancing carrier collection and reducing the recombination rate.

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior ION/IOFF ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.

In this paper, a graded channel doping paradigm is proposed to improve the nanoscale double gate junctionless DGJL MOSFET electrical performance. A careful mechanism study based on numerical investigation and a performance comparison between the proposed and conventional design is carried out. The device figures-of-merit, governing the switching and leakage current behavior are investigated in order to reveal the transistor electrical performance for ultra-low power consumption. It is found that the channel doping engineering feature has a profound implication in enhancing the device electrical performance. Moreover, the impact of the high-k gate dielectric on the device leakage performance is also analyzed. The results show that the proposed design with gate stacking demonstrates superior ION/IOFF ratio and lower leakage current as compared to the conventional counterpart. Our analysis highlights the good ability of the proposed design including a high-k gate dielectric for the reduction of the leakage current. These characteristics underline the distinctive electrical behavior of the proposed design and also suggest the possibility for bridging the gap between the high derived current capability and low leakage power. This makes the proposed GCD-DGJL MOSFET with gate stacking a potential alternative for high performance and ultra-low power consumption applications.