In this article, a novel sensitive encryption scheme to secure the digital images based on the Zaslavsky chaotic map is proposed. We employ the Zaslavsky chaotic map as a pseudo-random generator to produce the key encryption of the proposed image cryptosystem. The cipher structure has been chosen based on permutation-diffusion processes, where we adopt the classic permutation substitution network, which ensures both confusion and diffusion properties for the encrypted image. Our proposed algorithm has high sensitivity in plain image and the secret key. Moreover, the results show that the characteristics of our approach have excellent performance, with high scores (NPRC = 99.61%, UACI = 33.47%, entropy (CipherImage)  8, and correlation coefficient  0). Experimental results have been studied and analyzed in detail with various types of security analysis. These results demonstrate that our proposed cryptosystem has highly satisfactory security performance and can withstand various attacks compared to state-of-the-art methods.

In this paper, a new junctionless optical controlled field effect transistor (JL-OCFET) is proposed to improve the device performance as well as achieving low power consumption. An overall optical and electrical performances comparison of the proposed junctionless design and the conventional inversion mode structure (IM-OCFET) has been developed numerically, to assess the optical modulation behavior of the OCFET for low power optical interconnections applications. It is found that, the proposed design demonstrates excellent capability in decreasing the phototransistor power consumption for inter-chip optical communication application. Moreover, the proposed device offers superior sensitivity and ION/IOFF ratio, in addition to lower signal to noise ratio as compared to the conventional IM-OCFET structure. The obtained results indicate the crucial role of the junctionless (JL) design in enhancing the phototransistor performance and reducing the total power dissipation. Such a very sensitive OCFET can be very promising in the future low power optical receiver less compatible to CMOS modern technology for high-quality interchips data communication applications.

In this paper, a new junctionless optical controlled field effect transistor (JL-OCFET) is proposed to improve the device performance as well as achieving low power consumption. An overall optical and electrical performances comparison of the proposed junctionless design and the conventional inversion mode structure (IM-OCFET) has been developed numerically, to assess the optical modulation behavior of the OCFET for low power optical interconnections applications. It is found that, the proposed design demonstrates excellent capability in decreasing the phototransistor power consumption for inter-chip optical communication application. Moreover, the proposed device offers superior sensitivity and ION/IOFF ratio, in addition to lower signal to noise ratio as compared to the conventional IM-OCFET structure. The obtained results indicate the crucial role of the junctionless (JL) design in enhancing the phototransistor performance and reducing the total power dissipation. Such a very sensitive OCFET can be very promising in the future low power optical receiver less compatible to CMOS modern technology for high-quality interchips data communication applications.

In this paper, a new junctionless optical controlled field effect transistor (JL-OCFET) is proposed to improve the device performance as well as achieving low power consumption. An overall optical and electrical performances comparison of the proposed junctionless design and the conventional inversion mode structure (IM-OCFET) has been developed numerically, to assess the optical modulation behavior of the OCFET for low power optical interconnections applications. It is found that, the proposed design demonstrates excellent capability in decreasing the phototransistor power consumption for inter-chip optical communication application. Moreover, the proposed device offers superior sensitivity and ION/IOFF ratio, in addition to lower signal to noise ratio as compared to the conventional IM-OCFET structure. The obtained results indicate the crucial role of the junctionless (JL) design in enhancing the phototransistor performance and reducing the total power dissipation. Such a very sensitive OCFET can be very promising in the future low power optical receiver less compatible to CMOS modern technology for high-quality interchips data communication applications.

The use of uniformly doped channel, source and drain regions presents the well-known problem of the high series resistance associated to the extensions, which degrades the electrical performance of the nanoscale multi-gate junctionless MOSFETs. Therefore, new designs and accurate investigation of nanoscale double gate junctionless (DGJ) MOSFET including the defects at the interface Si/SiO2 are required for the comprehension of the fundamentals of such device behavior against the ageing phenomenon. Based on 2D numerical investigation of a nanoscale DGJ MOSFET, in the present work a numerical study for I-V and small signal characteristics, by including both the highly doped extension regions and the interfacial defects, is presented. The investigated design, which is a technologically feasible technique by introducing only one ion implantation step, provides a good solution to improve the device immunity against the interfacial defects under critical conditions, where the channel length is taken equals to 10 nm. In this context, I-V, analog and linearity characteristics are investigated by an appropriate 2-D numerical modeling, where the obtained results are compared with those of the conventional DGJ MOSFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The use of uniformly doped channel, source and drain regions presents the well-known problem of the high series resistance associated to the extensions, which degrades the electrical performance of the nanoscale multi-gate junctionless MOSFETs. Therefore, new designs and accurate investigation of nanoscale double gate junctionless (DGJ) MOSFET including the defects at the interface Si/SiO2 are required for the comprehension of the fundamentals of such device behavior against the ageing phenomenon. Based on 2D numerical investigation of a nanoscale DGJ MOSFET, in the present work a numerical study for I-V and small signal characteristics, by including both the highly doped extension regions and the interfacial defects, is presented. The investigated design, which is a technologically feasible technique by introducing only one ion implantation step, provides a good solution to improve the device immunity against the interfacial defects under critical conditions, where the channel length is taken equals to 10 nm. In this context, I-V, analog and linearity characteristics are investigated by an appropriate 2-D numerical modeling, where the obtained results are compared with those of the conventional DGJ MOSFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The use of uniformly doped channel, source and drain regions presents the well-known problem of the high series resistance associated to the extensions, which degrades the electrical performance of the nanoscale multi-gate junctionless MOSFETs. Therefore, new designs and accurate investigation of nanoscale double gate junctionless (DGJ) MOSFET including the defects at the interface Si/SiO2 are required for the comprehension of the fundamentals of such device behavior against the ageing phenomenon. Based on 2D numerical investigation of a nanoscale DGJ MOSFET, in the present work a numerical study for I-V and small signal characteristics, by including both the highly doped extension regions and the interfacial defects, is presented. The investigated design, which is a technologically feasible technique by introducing only one ion implantation step, provides a good solution to improve the device immunity against the interfacial defects under critical conditions, where the channel length is taken equals to 10 nm. In this context, I-V, analog and linearity characteristics are investigated by an appropriate 2-D numerical modeling, where the obtained results are compared with those of the conventional DGJ MOSFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The use of uniformly doped channel, source and drain regions presents the well-known problem of the high series resistance associated to the extensions, which degrades the electrical performance of the nanoscale multi-gate junctionless MOSFETs. Therefore, new designs and accurate investigation of nanoscale double gate junctionless (DGJ) MOSFET including the defects at the interface Si/SiO2 are required for the comprehension of the fundamentals of such device behavior against the ageing phenomenon. Based on 2D numerical investigation of a nanoscale DGJ MOSFET, in the present work a numerical study for I-V and small signal characteristics, by including both the highly doped extension regions and the interfacial defects, is presented. The investigated design, which is a technologically feasible technique by introducing only one ion implantation step, provides a good solution to improve the device immunity against the interfacial defects under critical conditions, where the channel length is taken equals to 10 nm. In this context, I-V, analog and linearity characteristics are investigated by an appropriate 2-D numerical modeling, where the obtained results are compared with those of the conventional DGJ MOSFETs. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)