Problems related to seepage through earth dams constitute more than 40% of the sources of observed damages throughout the world. A particular attention is given to how to minimize the effects due to seepage by using an adequate means of drainage to ensure the hydraulic and mechanical stabilities of the dam. In the homogeneous earth dams, the filtering drainage blanket is used with dimensions and location in the backfill determined by some unreliable methods. In this work a simple chart is developed in order to effectively locate the filtering drainage blanket along with a graph giving its length. This graph was obtained after having carried out a computer simulation of a great number of earth dams in which the total height, the embankment slopes, and the material characteristics were varied. For each dam, the drain length is changed within the acceptable limits of the hydraulic stability and the landslide stability of the downstream side embankment which is calculated.

Problems related to seepage through earth dams constitute more than 40% of the sources of observed damages throughout the world. A particular attention is given to how to minimize the effects due to seepage by using an adequate means of drainage to ensure the hydraulic and mechanical stabilities of the dam. In the homogeneous earth dams, the filtering drainage blanket is used with dimensions and location in the backfill determined by some unreliable methods. In this work a simple chart is developed in order to effectively locate the filtering drainage blanket along with a graph giving its length. This graph was obtained after having carried out a computer simulation of a great number of earth dams in which the total height, the embankment slopes, and the material characteristics were varied. For each dam, the drain length is changed within the acceptable limits of the hydraulic stability and the landslide stability of the downstream side embankment which is calculated.

We present in this paper a method for optimizing the design of CMOS bandgap voltage reference. The purpose of this work is to provide an optimal devices sizing, to reach the bandgap reference desired performances. This is achieved by using a simple mathematic calculations, basic layout design rules and simulation analyses. The proposed method is applied to design a voltage reference using CMOS 0.35uM process, featuring low temperature coefficient over the range of 105 °C, low noise, good power supply rejection in the range: 2.9 to 3.6 V, and keep an acceptable variation of the nominal value for a different process corners.

We present in this paper a method for optimizing the design of CMOS bandgap voltage reference. The purpose of this work is to provide an optimal devices sizing, to reach the bandgap reference desired performances. This is achieved by using a simple mathematic calculations, basic layout design rules and simulation analyses. The proposed method is applied to design a voltage reference using CMOS 0.35uM process, featuring low temperature coefficient over the range of 105 °C, low noise, good power supply rejection in the range: 2.9 to 3.6 V, and keep an acceptable variation of the nominal value for a different process corners.

We present in this paper a method for optimizing the design of CMOS bandgap voltage reference. The purpose of this work is to provide an optimal devices sizing, to reach the bandgap reference desired performances. This is achieved by using a simple mathematic calculations, basic layout design rules and simulation analyses. The proposed method is applied to design a voltage reference using CMOS 0.35uM process, featuring low temperature coefficient over the range of 105 °C, low noise, good power supply rejection in the range: 2.9 to 3.6 V, and keep an acceptable variation of the nominal value for a different process corners.

We present in this paper a method for optimizing the design of CMOS bandgap voltage reference. The purpose of this work is to provide an optimal devices sizing, to reach the bandgap reference desired performances. This is achieved by using a simple mathematic calculations, basic layout design rules and simulation analyses. The proposed method is applied to design a voltage reference using CMOS 0.35uM process, featuring low temperature coefficient over the range of 105 °C, low noise, good power supply rejection in the range: 2.9 to 3.6 V, and keep an acceptable variation of the nominal value for a different process corners.