This paper presents a full-wave method to calculate the resonant characteristics of rectangular microstrip antenna with and without dielectric cover, to explain the difference of performance with temperature between superconducting and normal conducting antenna. Especially the characteristics of high temperature superconducting (HTS) antenna were almost ideal around the critical temperature (Tc). The dyadic Green’s functions of the considered structure are efficiently determined in the vector Fourier transform domain. The effect of the superconductivity of the patch is taken into account using the concept of the complex resistive boundary condition. The computed results are found to be in good agreement with results obtained using other methods. Also, the effects of the superstrate on the resonant frequency and bandwidth of rectangular microstrip patch in a substrate–superstrate configuration are investigated. This type of configuration can be used for wider bandwidth by proper selection of superstrate thickness and its dielectric constants.

  The numerical homogenization technique is used in order to compute the effective elastic properties of heterogeneous random 2-phase composites.Differents microstructures are considered with different volume fraction.microstructure with random distribution of identical non-overlapping phases inclusions based on the Poisson process.(PBC), boundary conditions are applied on the representati ve volume element, RVE, of microstructures, for elastic modeling by finite element method. The aim of the work was to examine how spatial distribution and particles volume fraction influences the elastic  propertiesof the composite material. The results were compared to various analytical model

The paper proposes a new reliable fault-tolerant scheduling algorithm for real-time embedded systems. The proposed algorithm is based on static scheduling that allows to include the dependencies and the execution cost of tasks and data dependencies in its scheduling decisions. Our scheduling algorithm is dedicated to multi-bus heterogeneous architectures with multiple processors linked by several shared buses. This scheduling algorithm is considering only one bus fault caused by hardware faults and compensated by software redundancy solutions. The proposed algorithm is based on both active and passive backup copies to minimize the scheduling length of data on buses. In the experiments, the proposed methods are evaluated in terms of data scheduling length for a set of DSP benchmarks. The experimental results show the effectiveness of our technique.

Multi-Gate Junctionless MOSFETs are promising devices to overcome the undesired short channel effects for low cost nanoelectronic applications. However, the high series resistance associated to the source and drain extensions can arise as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance. Therefore, in order to obtain a global view of Double-Gate Junctionless (DGJ) MOSFET performance under critical conditions, new designs and models of nanoscale DGJ MOSFET including analog performance are important for the comprehension of the fundamentals of such device characteristics. In the present paper, a numerical investigation for the drain current and small signal characteristics is conducted for the DGJ MOSFET by including highly doped extension regions. The proposed approach, which is from a practical viewpoint a feasible technique by introducing only one ion implantation step, provides a good solution to improve the drain current, small signal parameters, analog/RF behavior and linearity of DGJ MOSFET for high performance analog applications. In this context, I–V and analog characteristics of the proposed design are investigated by 2-D numerical modeling and compared with conventional DGJ MOSFET characteristics.

The influence of gate dielectric materials on the performance of a carbon nanotube field-effect transistor has been studied by a numerical simulation model. This model is based on a two-dimensional nonequilibrium Green’s function formalism performed with the self-consistent solution of the Poisson and Schrödinger equations. The device performance is investigated in terms of leakage current, on-state current, ION/IOFF current ratio, subthreshold slope, drain-induced barrier lowering, as well as transconductance, drain conductance, and intrinsic gate delay. This study is carried out over a wide range of dielectric permittivities at low temperatures ranging from room temperature down to 100 K.

In this paper, the analytical investigation of a new design including drain and source extensions is presented to assess the electrical behavior of cylindrical gate-all-around junctionless (GAAJ) MOSFET for high performance RF and analog applications. Analytical models for drain current and performance parameters are derived incorporating the effect of two highly doped extension regions. Various analog and RF parameters like transconductance, cut-off frequency, drain current drivability, voltage gain and linearity characteristics have also been investigated. The proposed design shows excellent ability in improving the analog performance and provides a good solution to enhance the RF behavior and linearity of GAAJ MOSFET for low cost and high performance analog/RF applications. The proposed model results have been validated against the data obtained from a commercially available numerical device simulator. Moreover, the developed analytical approaches are easy to be implemented into microelectronic software simulators and therefore allow the study of the GAAJ-based deep submicron circuits

In this paper, we propose a new Double Gate Junctionless (DGJ) MOSFET design based on both gate material engineering and drain/source extensions. Analytical models for the long channel device associated to the drain current, analog and radio-frequency (RF) performance parameters are developed incorporating the impact of dual-material gate engineering and two highly doped extension regions on the analog/RF performance of DGJ MOSFET. The transistor performance figures-of-merit (FoM), governing the analog/RF behavior, have also been analyzed. The analog/RF performance is compared between the proposed design and a conventional DGJ MOSFET of similar dimensions, where the proposed device shows excellent ability in improving the analog/RF performance and provides higher drain current and improved figures-of-merit as compared to the conventional DGJ MOSFET. The obtained results have been validated against the data obtained from TCAD software for a wide range of design parameters. Moreover, the developed analytical models are used as mono-objective function to optimize the device analog/RF performance using Genetic Algorithms (GAs). In comparison with the reported numerical data for Inversion-Mode (IM) DG MOSFET, our optimized performance metrics for JL device exhibit enhancement over the reported data for IM device at the same channel length.

The back propagation (BP) algorithm has been very successful in training multilayer perceptron-based equalisers; despite its success BP convergence is still too slow. Within this paper we present a new approach to enhance the training efficiency of the multilayer perceptron-based equaliser (MLPE). Our approach consists on modifying the conventional back propagation algorithm, through creating an adaptive nonlinearity in the activation function. Experiment results evaluates the performance of the MLPE trained using the conventional BP and the improved back propagation with adaptive gain (IBPAG). Due to the adaptability of the activation function gain the nonlinear capacity and flexibility of the MLP is enhanced significantly. Therefore, the convergence properties of the proposed algorithm are more improved compared to the BP. The proposed algorithm achieves the best performance in the entire simulation experiments.