In this work, we present a comprehensive investigation of JL-GAA MOSFET including degradation-related ageing effects to study the nanoscale JL-GAA MOSFET reliability against the ageing phenomenon. A quantitative analysis of the device reliability behavior is carried out, in order to show the impact of the ageing effects on the device performance for digital applications. Moreover, the effect of the stress time on the device subthreshold behavior including the threshold voltage, DIBL and swing factor is elucidated, where the degradation related-ageing effects is represented by a new current generator in the opposite direction that describes the exponential degradation of the current as function of the stress time. Further, the role of introducing a high-k layer on the gate oxide in improving the JL-GAA MOSFET immunity against the degradation-related ageing effects is analyzed, where the proposed structure exhibits an excellent immunity against the ageing effects. In order to show the impact of the proposed approach on the nanoelectronic circuits designing, the developed model has been implemented to study the performance behavior of voltage amplifier circuit including degradation-related ageing effects. Therefore, the proposed approach can offer new insights regarding the investigation and simulation of the nanoelectronic circuits including the degradation-related ageing effects.

This paper presents a hybrid strategy combining compact analytical models of short channel Gate-All-Around Junctionless (GAAJ) MOSFET and metaheuristic-based approach for parameters optimization. The proposed GAAJ MOSFET design includes highly extension regions doping. The aim is to investigate the impact of this design on the RF and analog performances systematically and to show the immunity behavior against the short channel effects (SCEs) degradation. In this context, an analytical model via the meticulous solution of 2D Poisson equation, incorporating source/drain (S/D) extensions effect, has been developed and verified by comparing it with TCAD simulation results. A comparative evaluation between the proposed GAAJ MOSFET structure and the classical device in terms of RF/Analog performances is also investigated. The proposed design provides RF/Analog performances improvement. Furthermore, based on the presented analytical models, Genetic Algorithms (GA) optimization approach is used to optimize the design of S/D parameters. The optimized structure exhibits better performances, i.e., cut-off frequency and drive current are improved. Besides, it shows superior immunity behavior against the RF/Analog degradation due to the unwanted SCEs. The insights offered by the proposed paradigm will help to enlighten designer in future challenges facing the GAAJ MOSFET technology for high RF/analog applications.

In this paper a dynamic tracking control of mobile robot using neural network global fast sliding mode (NN-GFSM) is presented. The proposed strategy combines two control approaches, kinematic control and dynamic control. The laws of kinematic control are based on GFSM in order to determine the adequate velocities for the system stability in finite time. The dynamic controller combines two control techniques, the GFSM to stabilize the velocities errors, and a neural network controller in order to approximate a nonlinear function and to deal the disturbances. This dynamic controller allows the robots to follow the desired trajectory even in the presence of disturbances. The designed controller is dynamically simulated by using Matlab/ Simulink and the simulations results show the efficiency and robustness of the proposed control strategy.

In this paper, the method for the nonlinear control design of a permanent magnet synchronous generator based-wind energy conversion system (WECS) is proposed in order to obtain robustness against disturbances and harvest a maximum power from a typical stochastic wind environment. The technique overcomes both the problem of nonlinearity and the uncertainty of the parameter compared to such classical control designs based on traditional control techniques. The method is based on the differential geometric feedback linearization technique (DGT) and the Lyapunov theory. The results obtained show the effectiveness and performance of the proposed approach.

In this paper, channel doping engineering aspect is proposed as a new way to improve the junctionless Gate All Around (GAA) MOSFET performance for digital and analog applications. The amended channel doping consists of a lateral graded profile, where the channel is divided into two regions with different doping levels. Analytical approaches for the drain current, leakage power, digital and small signal parameters are developed incorporating the impact of graded channel doping (GCD) paradigm on the device electrical behavior. Exhaustive study based on a performance comparison between the proposed structure and the conventional one is carried out, where the proposed design exhibits a good capability in improving the overall device figures-of-merit (FoMs), governing the leakage and the analog performance. More importantly, Particle Swarm Optimization (PSO) approach is proposed as a metaheuristic technique to boost the device performance through carefully adjusting the design parameters of the proposed GCD feature. It is found that the optimized design outperforms considerably the conventional counterpart and enable making wise trade-offs, where an enhancement of 300% in the I ON /I OFF ratio, 482% in the intrinsic gain, and 340% in the cut-off frequency has been reached. Besides, the proposed design provides a sufficient capability for suppression of the leakage effects. The obtained results underline the distinctive property of the proposed design for bridging the gap between high analog and digital performances with ultra-low power consumption. This makes the proposed design a potential alternative for ultra-low power and high electrical performance applications.

In this work, versatile CdS/Cu 2 ZnSnS 4 (CZTS) solar cell designs based on intermediate metallic sub-layers (Au, Ti, and Ag) engineering are proposed for enhancing light-scattering behavior and reducing recombination losses. The idea behind this work is to generate optical confinement regions in the CZTS absorber layer to achieve an improved absorption and appropriate antireflection effects. Moreover, the ultra-thin metal at the CZTS/Mo interface can be helpful for reducing the series resistance, where it behaves like a blocking layer for the Sulfur diffusion. We further combine the proposed designs with Particle Swarm Optimization (PSO)-based approach to achieve broadband absorption and boost the conversion efficiency. It is found that the optimized design with Ti sub-layer improves the CZTS solar cell properties, where it yields 31% improvement in short-circuit current and 60% in the power efficiency over the conventional one. Therefore, the optimized designs provide the opportunity for bridging the gap between improving the optical behavior and reducing the recombination losses.

In this paper, the role of introducing an intermediate Indium Tin Oxide (ITO) thin-film in improving the Au/Si Schottky Barrier Diodes (SBDs) electrical performance is experimentally analyzed. The Au/ITO/Si/Au structures with different ITO thicknesses were fabricated using RF magnetron sputtering technique. The current-voltage (I-V) characteristics of the investigated structures are analyzed, where the device electrical parameters are extracted. It is found that the introduced ITO thin-film has a significant impact in reducing the ideality factor (n=1.25), the interfacial defects (Nss=1.5×1012 eV-1cm-2) and the series resistance (Rs=32Ω). Our study demonstrates that the use of ITO intermediate thin-film can generate minority carrier injection effects, which lead to achieve the dual role of enhanced derived current and lower series resistance. Moreover, the structure thermal stability behavior is investigated and compared with those of the conventional design in order to reveal the device reliability against the thermal variation. Furthermore, the effect of the annealing on the device thermal stability is also analyzed. Our investigation shows that the annealed structure provides the possibility for avoiding the degradation related-heating effects. Therefore, the proposed Au/ITO/Si/Au structure offers the opportunity for bridging the gap between achieving superior electrical performance and enhanced thermal stability. The obtained results may facilitate the design of high-performance SBDs for sensing and microelectronic applications.

In this paper, graded Ge mole fraction aspect is proposed as a new way to achieve the dual benefit of improved Si/SiGe-based solar cell photoconversion efficiency and suppressed degradation related-dislocation effects. Our purpose resides mainly on decreasing the defect density at the Si/SiGe interface through shifting the Ge concentration gradually with the SiGe absorber layer thickness. Further, a careful mechanism analysis based on investigating numerically the impact of the proposed graded Ge content paradigm on reducing the degradation related-dislocation effect is performed. The advantage of using a SiGe layer with graded Ge concentration instead of a thin-film SiGe alloys is presented. Moreover, the impact of the proposed SiGe layer thickness on the solar cell conversion efficiency is carried out. It is found that the proposed feature brings the opportunity of reducing the lattice mismatch at the Si/SiGe interface, which can in turn improve the Si/SiGe-based solar cell conversion efficiency. In addition, increasing the Ge content progressively suggests the band-gap modulation aspect that enables improving the solar cell optical absorption and the total resistance. Therefore, the proposed design pinpoints a new path toward avoiding recombination losses through suppressing the degradation related-dislocation effects, which makes it potential alternative for providing high-efficiency Si-based solar cells.

In this paper, a new nanoscale double-gate junctionless tunneling field-effect transistor (DG-JL TFET) based on a Si1-xGex/Si/Ge heterojunction (HJ) structure is proposed to achieve an improved electrical performance. The effect of introducing the Si1-xGex material at the source side on improving the subthreshold behavior of the DG-JL TFET and on suppressing ambipolar conduction is investigated. Moreover, the impact of the Ge mole fraction in the proposed Si1-xGex source region on the electrical figures of merit (FoMs) of the transistor, including the swing factor and the ION/IOFF ratio is analyzed. It is found that the optimized design with 60 atom % of Ge offers improved switching behavior and enhanced derived current capability at the nanoscale level, with a swing factor of 42 mV/dec and an ION/IOFF ratio of 115 dB. Further, the scaling capability of the proposed Si1-xGex/Si/Ge DG-HJ-JL TFET structure is investigated and compared to that of a conventional Ge-DG-JL TFET design, where the optimized design exhibits an improved switching behavior at the nanoscale level. These results make the optimized device suitable for designing digital circuit for high-performance nanoelectronic applications.